1. Field of the Invention
The invention relates to a flat panel display (FPD), and in particular to a pixel structure for a low temperature polysilicon type FPD capable of increasing capacitance of the storage capacitor and a method for fabricating the same.
2. Description of the Related Art
Due to the advantages of thin profile and low power consumption, liquid crystal displays (LCDs) are widely employed in electronic products, such as portable personal computers, digital cameras, mobile phones and the like. During the fabrication of LCD pixels, however, several lithography processes are required, such that the manufacturing process is complex and costs are increased.
FIGS. 1A to 1F illustrate a conventional method for fabricating a pixel structure of a low temperature polysilicon type LCD. In FIG. 1A, a transparent substrate 100 comprising a transistor region 10 and a capacitor region 20 is provided. Semiconductor layers 102 and 104 are formed on the transistor region 10 and the capacitor region 20 of the substrate 100, respectively, by conventional deposition, lithography and etching. The semiconductor layer 102 formed on the transistor region 10 serves as an active or channel layer for a thin film transistor.
As shown in FIG. 1B, an insulating layer 106 is formed on the substrate 100 and covers the semiconductor layers 102 and 104, in which the insulating layer 106 formed in the transistor region 10 serves as a gate dielectric layer. Next, a metal layer (not shown) is formed on the insulating layer, and is then patterned by lithography and etching, to form a gate electrode 108 overlying the semiconductor layer 102 and a lower metal layer 110 overlying the semiconductor layer 104. Ion implantation 111 is subsequently performed to form source/drain regions 102a and a channel region 102b in the semiconductor layer 102.
As shown in FIG. 1C, an interlayer dielectric (ILD) layer 112 is deposited on the insulating layer 106 and covers the gate electrode 108 and the lower metal layer 110. Thereafter, contact openings 112a are formed in the ILD layer 112 to expose the source/drain regions 102a. The ILD layer 112 in the capacitor region 20 serves as a capacitor dielectric layer for a storage capacitor.
As shown in FIG. 1D, a metal layer (not shown) is formed on the ILD layer 112 and fills the contact openings 112a. Next, the metal layer is patterned by lithography and etching, to form source/drain electrodes 114 on the semiconductor layer 102 and an upper metal layer 116 overlying the lower metal layer 110.
Next, a planarization layer (protective layer) 120 is formed on the ILD layer 112 and covers the source/drain electrodes 114 and the upper metal layer 116. A contact opening 120a is subsequently formed in the planarization layer 120 in the transistor region 10 by lithography and etching, to expose one of the source/drain regions 114, as shown in FIG. 1E. Next, a transparent conductive layer (not shown) is formed on the planarization layer 120 and fills the contact opening 120a. The transparent conductive layer is subsequently patterned by lithography and etching, to form a pixel electrode 122, as shown in FIG. 1F.
In such a pixel structure, at least six costly and complex lithography steps are required. Besides, since the semiconductor layer 104 cannot serve as a capacitor electrode, a thicker ILD layer 112 is served as a capacitor dielectric layer to replace the thinner insulating layer 106. As a result, capacitance of the storage capacitor is reduced.
In order to solve the described problems, there exists a need in the art for development of an improved pixel structure which can reduce the manufacturing cost and increase the capacitance of the storage capacitor.